Comprehensive hot carrier mechanism investigation of 40V LDNMOS transistor

To reveal the hot carrier induced degradation (HCI) mechanism of 40 V lateral-diffused NMOS, TCAD simulation was firstly performed to predict the impact ionization strength and distribution along the lateral direction. IV characteristic curve measurements were subsequently performed to monitor Id
_s
and R
_on
shift to offer a preliminary explanation towards the physical mechanism of degradation. Meanwhile, a strong positive correlation between I
_sub
and R
_on
degradation was observed experimentally. Hence, I
_sub
could be a promising index for HCI immunity evaluation in predicting time-to-failure (TTF) upon R
_on
degradation. Charge pumping technique was also performed to precisely identify the location and quantity of interface states during DC electric stressing. A comprehensive investigation of hot carrier degradation mechanism was clarified and reported in this paper. Eventually, hot carrier safe-operation-area (SOA) is defined for evaluating the performance of the LDMOS transistors and for circuit designers' reference.