Dynamic Co-operative Intelligent Memory

As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many methods, for example, cache, Massively Parallel Processor (MPP) and interleaved memory have been developed. However, computer system performance fails to make reasonable improvement in the data intensive applications, due to the long latency and limited bandwidth. In a continuing effort to bridge this widening gap between processor and main memory speed, a new concept called Processor-In-Memory (PIM) is introduced, which capitalises on merging the processor unit with its memory unit on the same chip. Several architectures based on this concept have been proposed such as, IRAM, Active Pages, FlexRAM, Computational RAM, etc. The most immediate benefit provided by these architectures is the increased on chip bandwidth and low memory latency. These architectures have some limitations such as their adaptability, scalability and cost-effectiveness. In this paper, a Dynamic Cooperative Intelligent Memory (DCIM) architecture is presented, where some of those limitations are bridged.