Design of a 2D Mesh-Torus Router for Network on Chip

New systems on chip (SoC) design allow one to build heterogeneous systems with several functional units, distributed memories, and interconnections on the same chip. In order to achieve more reuse, flexibility, and performance, bus based interconnections are no more sufficient and Network on Chip concepts are emerged. This paper presents the design of a scalable packet based router allowing data transfer and managing dynamically several communications in parallel. The designed router, described in VHDL on RTL level, was simulated in the case of topologies 2D- mesh and 2D-torus (2x2), (3x3) and then (4x4). The used design methodology is based on VHDL as a description language, simulation and synthesis tools.