Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is important to characterize the intrinsic MOSFET mismatch accurately. In this paper, test structures are designed to study the influence of back end of line (BEOL), multi-fingered layout, and gate protection diode (GPD) on MOSFET threshold voltage mismatch characterization.