Implementation of picture sequence output in H.264 decoder based on FPGA

The new international video coding standard H.264 has used lots of new algorithms in video coding theory. Comparing with other exiting standards, H.264 has better coding efficiency and transmitting reliability. The H.264 decoder mentioned in this paper matches the baseline level of H.264, and is designed as a video decoder in a network video meeting device. A picture sequence output process locates at the end of the H.264 decoding workflow. Designed based on FPGA using a top-to-bottom method, the picture sequence output module manages the storage and calculates the output order of decoded pictures. This design is implemented in VerilogHDL, and has passed the RTL level simulation and function test. Being verified on XC3S2000 FPGA test platform, all modules in this design can satisfy the video quality and decoding speed requirements of network video meeting, of which the display resolution is 352x288 and the frame rate is 25fps.