Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $\kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO
₂
low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I
_min
is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO
₂
gate dielectric and fluorine preimplantation can simultaneously achieve low V
_TH
~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I
_ON
/I
_min
current ratio ~1.98 times 10
⁷
.