Fast FPGA-Based Delay Estimation for a Novel Hardware/Software Partitioning Scheme

In this paper a fast and accurate delay estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware as a single implementation, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the area and latency ranges for different hardware implementations. The presented tool estimates the delay for these two hardware alternatives. Our delay modeling technique accounts for both the logic and routing delays so as to minimize the estimation error. The computational cost of the presented estimation tool depends linearly on the design complexity, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate with an average error of 4.2%.