Chip Power Interconnection

This paper describes recent developments made to the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realised. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasised. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool. The aim of this paper is to improve reliability of chip interconnection and to increase durability of these structures.