0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers

For the first time, we report on deep sub-micron (gate length down to 0.12μm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cut™ process to fabricate 200mm GeOI wafers with Ge thickness down to 60nm. A full CMOS compatible p-MOSFET process was implemented with HfO
2
/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I
ON
, I
OFF
, G
m
, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.