A Cycle-Stealing Technique for Pipelined Instruction Decompression System for Embedded Microprocessors

For instruction decompression, many techniques have been developed. However, when branching and cache missing occur, they may either incur delays to refill buffers or sacrifice the compression ratio or slow down the clock rate. This paper presents a new technique based on cycle-stealing technique to eliminate all these defects. The simulation results for several benchmarks show that the average compression ratio, the hardware cost and the speed are all better than other techniques.