CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC

The results of design and simulation of a novel architecture for a 10 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the serializer/deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 mum CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.