Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management

The power of 3 different power domains is managed by continuous co-locking of voltage and clock, dynamically varying clock frequency and supply voltage level from 90MHz to 200MHz and from 1.0V to 1.8V, respectively. A test 3D-graphics SoC is divided into 3 power domains and their power are managed separately. The workload of each domain is the control parameter to each power management unit (PMU). It takes 0.45mm
²
with 0.18μm CMOS process and consumes 5mW. Total SoC takes 17.2 mm
²
and consumes 52.4mW at full operation with triple domains power management.