Evolving virtual reconfigurable circuit for a fault tolerant system

This paper describes about the design and implementation of a virtual reconfigurable circuit (VRC) for a fault tolerant system which averages the (three) sensor inputs. It deals with evolving the desired circuit by decoding the configuration bit streams uploaded into its SRAM. The circuits that are successfully evolved in this system is, corresponds to different situation such as (i) all three sensors are faultless (ii) one of the input sensor fails as open. The objective of this work is to decode the configuration bit streams and thereby evolving the desired optimal circuit in the VRC and also to obtain the power consumed by the VRC.