Room-temperature bias acceleration test for data retention screening on SONOS nonvolatile memory devices

We demonstrated a significant charge loss by a small DC bias applied to the SONOS gate. This charge loss can be correlated with that of a high-temperature bake. A bias acceleration test can be useful for wafer-level retention screening. The results also suggest that the gate bias for data readshould be set around 0V to minimize the gate read disturbance. More work is underway to investigate the mechanism of charge loss, the recall disturbance in nvSRAM, etc.