Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

V
_t
variability in FinFET SRAM is evaluated for the first time by direct measurement of the cell transistors down to 25 nm gate length. By taking the V, mismatch between Pull-Down transistors (PD) or between PD & Pass Gate transistor (PG), the dependence of V, variability on the cell transistor layout and channel impurity concentration was clearly observed. Read / Write margins in FinFET SRAM cell are also investigated by measuring both N-curves and their variability. The results suggest that FinFET is still a promising candidate for SRAM applications even in 32 nm node and beyond, if the appropriate cell design is applied.