High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

This paper describes the fabrication and performance of CMOS transistors featuring Flash Lamp Annealing (FLA) for 45nm node. We show, for the first time, applying FLA prior to Spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused by implantation and suppresses the Transient Enhanced Diffusion (TED). These improvements result in 11% and 8% higher saturation drive current, and IDSAT=750μA/μm and 1160μA/μm for IOFF=100nA/μm at Vdd=1V in PFET and NFET, respectively. We also report the pattern density dependence of performance gain from FLA technique.