Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction

The scaling limit of planar bulk MOSFETs with ultra-shallow junction (USJ) by using diffusion-less high-activation annealing technique has been investigated. Incorporation of cluster-ion (B
₁₈
H
₂₂
) implantation for PFETs and high-temperature msec-annealing, where the dedicated fabrication-process was redesigned including multiple halo implantation and thin SD-silicidation, enables us to examine near-scaling limit bulk CMOS device performance with ultimately shallow junction (5-15 nm). Techniques developed here to overcome trade-off between the functionable minimum gate length (L
_min
) and on-current (I
_on
, including suppression of surface-recess on S/D extension, higher activation of S/D-extension with optimized msec-annealing condition and the resistance reduction with optimized spacing of the bottleneck at the joint of S/D-ext and deep-S/D junction. Those techniques highly contribute device performance enhancement by effectively reducing large parasitic resistance due to extremely shallow X
_j
. Theoretical estimation implies that fully low parasitic resistance, thin T
_inv
and ultimately shallow X
_j
extend L
_min
scaling to about 20 nm for planar bulk CMOSFET.