FPGA design and implementation of carrier synchronization for DVB-S2 demodulators

Carrier synchronization in DVB-S2 demodulators is a challenging design issue due to advanced coding scheme and high order amplitude and phase shift keying (APSK). We present an FPGA-based circuit implementation, which is low-complexity and robust to frequency offset. The design comprises three frequency and phase synchronizers, employing modified L&R, ML and modified digital PLL algorithms. Algorithm-to-architecture mapping is also examined in detail to achieve optimized structure and performance. Implemented in Altera Stratix II EP2S60 FPGA, the scheme is applied to all 4 pilot-inserted modulation modes in the DVB-S2 standard at 25 MBaud, acquiring up to 100 kHz frequency offset.