A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector

A 2.5-Gb/s clock and data recovery (CDR) circuit, which incorporates dual loop architecture with half-rate linear phase detector and digital quadricorrelator frequency detector (DQFD) was present in this paper. The circuit is implemented under 0.13 mum CMOS process with the core chip area of 350 mum*110 mum. The HSPICE simulation results show that the center frequency of the voltage-controlled oscillator (VCO) is 1.25 GHz, the lock time is less than 5 mus, the operation range is from 2.20 Gbps to 2.83 Gbps, and the power consumption is about 15.2 mW at supply voltage of 1.2 V.