K-4 Video compression LSI: Past, present, and future trends

In 1995, MPEG-2 became a video coding international standard. Since then, a wide variety of video compression LSIs have been developed and actually deployed in many applications such as digital HDTV broadcasting, TV conference, mobile and so forth. Since video coding technology is essential to the efficient storage and transmission of video data, it continues to play an important role in ubiquitous (anywhere, anytime, etc) and coming ambient (safe, comfortable, etc) information society. In this talk, I will provide video compression LSI technologies from past, present and future points of view. The MPEG-2 encoder chip set and the video communication PC board developed by NTT (Nippon Telegraph and Telephone Corporation) in 1996 is picked up as a pioneer work in the history of a video compression LSI. Academia and industry LSI trends based on international conference publications and commercial products are also shown. As a current hot topic, a H.264/AVC encoder SoC for HDTV 1080p at 30fps is introduced. It is implemented with the dedicated hardware engines and a 32-bit Media embedded Processor (MeP). Three hardware engines for integer motion estimation (IME), fractional motion estimation (FME) and intra prediction (IP) greatly enhance the processing efficiency at far lower hardware cost. 11.5Gbps 64Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth and reduce the external I/O power consumption. A 200 MHz 64-bit AMBA AHB system bus integrates the MeP, IME, FME and IP engines with the 64Mb System-in-Silicon DRAM. The SoC core occupies 27.1mm2 die with 0. Bum CMOS technology and dissipates 1.41W at 1.8V and 200MHz. As future trends, let me talk two directions that I believe important: a low power LSI based on a low complexity video compression algorithm and a media-codec-centric application SoC.