A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain

A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bit-block, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 mum CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.