Jitter analysis of electrical samplers based on a propagation line

The aim of this paper is to demonstrate the good jitter performances of samplers based on a propagation line. Targeting high resolution and high bandwidth (10 effective bits at 8 GM and 20 GM bandwidth) two of these architectures have been adapted to large temporal sampling windows. As the trigger structures consist of inverters, the jitter of an elementary inverter is optimized and a delay cell is simulated and compared to measurements. Jitter of the two trigger structures is discussed.