Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

S-parameter test structures show total capacitances per perimeter of ESD diodes increased from ~0.42fF/mum in 90nm technologies to ~0.7fF/mum in 65nm and 45nm technologies. To achieve lower capacitances for high frequency circuits, layout and process optimization are needed. SCR devices from a 45nm technology show ~0.32fF/mum and can be used for circuit applications with stringent capacitance requirement. Two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.