A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions

We address the challenge of implementing reliable computation of Boolean functions in future nanocircuit fabrics. Such fabrics are projected to have very high defect rates. We overcome this limitation by using a combination of cheap but unreliable nanodevices and reliable but expensive CMOS devices. The contribution of this work is twofold - (1) A heterogeneous architecture suitable for low level defect tolerance (2) A novel coding strategy that for the first time exploited the structure of Boolean function for better coder. In our approach, defect tolerance is achieved through a novel coding of Boolean functions; specifically, we exploit the don’t cares of Boolean functions encountered in multi-level Boolean logic networks for constructing better codes. The optimal coding problem is NPhard. We solved it with a SAT based heuristic. We show that compared to direct application of existing coding techniques, the coding overhead in terms of extra bits can be reduced, on average by 23%, and savings can go up to 34%. We demonstrate that by incorporating efficient coding techniques more than a 20% average yield improvement is possible in case of 10% defect rates. We incur a negligible delay penalty of less than 1% for decoder and the area is 13X smaller compared 22nm CMOS technology and 32% smaller than TMR (triple modular redundancy) coding scheme.