Minimizing leakage power in sequential circuits by using mixed vt flip-flops

Dual V
t
has been widely used to control leakage, while, at the same time, satisfying circuit performance. However, current approaches target the combinational circuits even though sequential elements, such as flip-flops and latches, contribute an appreciable proportion of the total leakage. The use of dual V
t
flip-flops is limited to circuits of large timing slack, because introducing high V
t
flip-flops in place of low V
t
ones yields abrupt change in timing. We propose mixed V
t
flip-flops, which are designed by using both low and high V
t
, but in different transistors. Compared to low V
t
flip-flop, the mixed V
t
flip-flops exhibit increased delay, but either on setup time or on clock-to- Q delay but not on both, while their leakage is greatly reduced. We extend the conventional sensitivity-based dual Vt allocation algorithm to incorporate mixed V
t
flip-flops together with dual V
t
combinational gates. Experimental results show that an average leakage saving of 31% is achieved, compared to the use of dual V
t
on combinational subcircuits alone. The leakage of the flip-flops themselves is cut by 57% on average.