A 1.5V Low Power CMOS LNA Design

A 1. 5 V 0.18mum CMOS LNA for GPS applications has been designed with fully differential topology. Under such a low supply voltage, the fully differential LNA has been simulated, it provides a series of good results in Noise figure, Linearity and Power consumption. The LNA achieves a Noise figure of 1. 5 dB, voltage gain of 32 dB, Power dissipation of 6 mW, and the input reflection coefficient (S
_n
) is -23 dB.