Fault-Tolerance CMP Architecture based on SMT Technology

In order to improve the reliability of the single-chip multi-processor (CMP), this paper proposes a fault- tolerant CMP architecture which combines with the simultaneous multi-threading (SMT) technology so as to implement the transient fault detection and to automatically accomplish the thread-level recovery. The architecture, through adopting a simple strategies and a little extra hardware to implement the functionality of fault tolerance, attains a wider coverage of the fault and improves the performance of the fault-tolerant CMP.