Advanced high-K/metal gate charge trapping memories for post-45 nm node

We present our recent results on charge trapping memory arrays with HfSiO
_x
high -K dielectrics and TiN as the metal gate aimed at low power/low voltage embedded flash and E
²
PROM applications. HfSiO
_x
/SiN memory arrays operated with moderately low program/erase voltages, with an excellent endurance and good retention up to 85°C are demonstrated.