Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3- dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient V
TH
window margin of 2 V.