Locating a High-Volume Memory Device Fabrication Facility: A Global Study

This project assessed the costs associated with wafer fabrication and developed a heuristic for general semiconductor site decisions. After studying several theoretical models, the Capstone team used discrete choice analysis and the multinomial conditional logit model for its evaluation. Using empirical research, the team identified a set of variables that may have influenced past location decisions. These variables were used in the model to compare the likelihood of locating in one country among a set of possible choices. The team approximated the conditional logit model with the statistical package SAS/STAT and assessed the results for statistical merit and possible conclusions. The completed analytical framework identified capital subsidies, water availability, and labor quality as the influential variables based on statistical significance. This project is a joint effort between student teams from the Darden School of Business and the School of Engineering and Applied Science at the University of Virginia.