Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 10
²⁴
times10
²⁴
-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum
²
and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.