Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate noise generated by the switching digital part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called "digital substrate noise" on a 0.13-μm SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.