Optimizing Floating Body Effect & AC performance in 65nm PD-SOI CMOS

An advanced partially-depleted (PD) silicon-on-insulator (SOI) CMOS device was optimized with full consideration of the floating body effect (FBE) using channel and S/D engineering. By adjusting channel and S/D implants' species and dosage, the S/D doping profiles across transistor sidewall junction will be shown to reduce floating body effects and sidewall junction capacitance. Reduced sidewall junction capacitance results in higher performance in AC operation. In this paper we successfully demonstrated the optimized devices that exhibit suppression floating body effect, and lower ring oscillator (RO) static leakage and active power consumption at the same propagation delay.