A Novel Incremental Floorplan Algorithm for Duplication in Integration of High-level Synthesis and Floorplan

With VLSI advancing into deep submicron technology stage, interconnection delay has been the dominated aspect of timing issues. In this paper, we contrive a duplication method in high-level synthesis for interconnect delay optimization and present a new incremental floorplan algorithm integrating high-level synthesis with floorplan for exerting those duplication schemes. The new algorithm has been proved by experiments significantly decreasing the total wirelength and the critical path wirelength over the initial results with a linear time complexity. At the same time, the area has increased slightly and the area usage is even improved.