Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 Matrix processors reduced 45% power consumption. The performance-oriented multi-bank Matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The IGHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.