A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC

A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves a measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm
²
, and consumes 2.54mW from a 1.62V supply. The measured dynamic range figure of merit is 174dB.