A 2.4GHz CMOS VCO Design

A single resistor was used between the drain node of the bias transistor and the source node of the differential transistors. The wide-band nature of resistance can suppress the 2nd harmonic as well as other even harmonics leaking from the LC tank across the full period of oscillation. A fully integrated 2.4 GHz all PMOS LC VCO was implemented in a 0.35 mum CMOS process. The simulation results show the achieved phase noise of -121dBc/Hz@600 kHz.