Radiation Hardened CMNOS/SOS Mask Programmable Rom and General Processor Unit

A low temperature CMOS/SOS process has been developed to minimize threshold voltage shifts and back channel leakage currents caused by radiation and temperature-bias stress conditions. Dual dielectric gate structures using CVD nitride 1300A thick on thermally grown SiO2 100A thick have been used to minimize the oxidation time at high temperatures. The dual dielectric structure has been combined with a multiple boron ion implant, ϕ = 3.5 × l012 cm-2 at implant energies of 180 keV and 80 keV to produce n-channel enhancement devices with a graded boron profile with a maximum near the Al2O3-Si interface. This process has been utilized to fabricate a 1024 bit mask-programmable ROM (MP/ROM) and general processor unit (GPU). This paper will discuss the organization and fabrication of the MP/ROM and GPU and present data for radiation hardness tests to both accumulated total dose and transient upset radiation environments at levels of 1 × 106 rad (Si) and > 1010 rad (Si)/sec (narrow pulse), resepectively. Temperature bias stress data is presented which demonstrates device stability.