Noise Isolation Modeling and Experimental Validation of Power Distribution Network in Chip-Package

This paper models the chip and the package power distribution network in the simplified SPICE-level. The model is successfully validated by experiments using Vector Network Analyzer. By using the SPICE-level model, the noise isolation between the noise current source at the chip and the power distribution network at the package is analyzed from 1 MHz to 3 GHz. The contribution of each part in the power distribution network is also analyzed by experiments. The transfer impedances are simulated and measured the power distribution network between the chip and the package varying with the wire- bond and the on-package decoupling capacitor, case by case.