Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic

In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and noise margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the noise margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned noise margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the noise margin. Therefore, this delay model simply relates the speed performance, the power consumption and the noise margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-noise margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.