Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate

We have investigated Al2O3, Dy2O3, and La2O3 as dielectric cap layers for use in low Vt CMOS integration schemes. The cap layers are found to reduce the Vt by 0.2 V for pFET, and with 0.2 V and 0.5 V for nFET, respectively. Subsequently, we report on the benefits of performing the nitridation (by means of DPN) after cap deposition, instead of before. This allows better control of the nitrogen profile in the stack, resulting in improvement of Vt reduction, Vt wafer uniformity, mobility and BTI characteristics. Finally, we observe that the Vt shift induced by the dielectric cap layer significantly depends on the N-content of the metal gate. After reporting on these three key stack characteristics, we propose two practical single metal CMOS integration schemes.