JPEG Hardware Accelerator Design for FPGA

A fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the accelerator accepts 8×8 image blocks in a streaming fashion, and outputs the zigzag-scanned, quantized 2D DCT coefficients of the block. The decoder part accepts zigzag-scanned, quantized DCT coefficients, and outputs reconstructed 8×8 image block. Each part has a throughput of one system clock per pixel per channel. The encoder employs a fast pipelined implementation for 2D DCT (LK.C. Agonstini et al., 2001). For the decoder, a new pipelined 2D IDCT structure is developed. Our IDCT structure is based on an IDCT factorization for software implementation, and is inspired by the pipelined DCT structure employed in the encoder. The resource utilization and maximum frequency figures for a particular FPGA target suggest that our accelerator has competitive performance.