On Adapting Power Estimation Models for Embedded Soft-Core Processors

The increasing use of battery-powered embedded systems has motivated the development of power consumption models in order to help designers to build low-power systems. Due to the configurability features of FPGAs, the adoption of systems containing one or more soft-core processors on a single chip is becoming more and more attractive. This paper presents an adaptation of the instruction-level power estimation model to soft-core processors implemented in FPGAs. This model allowed to estimate the power dissipated in eleven test applications with a maximum error of 4.78%. The Ongoing work includes efforts towards a software power estimation model for multi-core systems embedded in a single FPGA device.