Improvement of a 4-mask Process Recipe

A fabrication process used by SJSU was altered in order to lower the threshold voltage, VT. This was done to allow the fabrication process to be used for analog integrated circuit design for future EE classes. Wafers fabricated from previous semesters using the same process recipe were measured to have about a 4-5 V threshold voltage on average. The Athena process simulator was used to observe VT for different times and temperatures of the substrate diffusion step of boron. After simulations, the times for substrate diffusion used to carry out the fabrication process were chosen to be 180, 240 (unchanged), and 300 minutes while the temperature remained unchanged. For the 180, 240, and 300 minute diffusion times, Athena measured VT to be 1.21, 1.16, and 1.12 V respectively. The fabrication process was then carried out for the three different diffusion times in SJSU's IC fabrication lab. Once fabrication was completed, the wafers were measured for their alignment, gate oxide thickness, transconductance, channel length modulation, body effect, effective length, and threshold voltage. From the fabricated wafers the average VT measured for each diffusion time was 3.54, 3.08, and 2.15 V for 180, 240, and 300 minute diffusion times, respectively. When extracting Vt, the oxide interface charge, Qi, may have been assumed to be too high for the simulations (5times10
¹¹
cm
^-3
). These results show that the EE/MatE 129 recipe may need to use a dopant with a smaller boron concentration or the boron diffusion step before the growth of the field oxide may need to be removed in order to reduce the substrate concentration.