Chip Design of LPC-cepstrum for Speech Recognition

This paper proposed an ASIC of LPC-cepstrum (LPCC) for speech recognition. The proposed ASIC of LPCC can reduce the calculation load of processor in the speech recognition system. In addition, the resource sharing method is adopted into our design in order to reduce the chip size. Hence, it does not give an emphasis on sophistication but on high- performance and low-cost solution. Finally, we did some experiments to compare with other DSP or ASIC design. We found that our proposed LPCC ASIC can efficiently reduce the computation load.