A Novel Power Optimization Technique for Ultra-Low Power RFICs

This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the g
_m
f
_T
-to-current ratio (g
_m
f
_T
/I
_D
), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the g
_m
f
_T
/I
_D
reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18μm process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100μW.