Coherent BPSK Demodulator MMIC Using an Anti-Parallel Synchronization Loop

A coherent BPSK demodulator using an anti-parallel synchronization loop is successfully implemented in a 0.18 μm CMOS monolithic-microwave-integrated-circuit (MMIC). Due to the novel concept of the anti-parallel synchronization method, the demodulator only requires a differential VCO as opposed to a quadrature VCO as in the Costas Loop, thereby saving considerable chip space. The fabricated demodulator works at a carrier frequency of 2.7GHz and has been tested at data rates of up to 7Mbps. The circuit measures 1.0 mm
²
including the bonding pads and consumes 151 mW of power.