Distortion Simulations with the PSP Model: Common-Gate Circuits

We present extensive simulations of distortion in common-gate configured FETs, operated around Vds=0V, using the new PSP MOSFET model. Results are compared to measurements. We show that as a FET is configured into an increasingly more realistic circuit, that the PSP models distortion performance improves correspondingly and that it can predict intermodulation distortion within 3dB of measured data. Third, we quantify, for the first time, to what extent the intermodulation distortion, as represented by IIP3, can be improved by increasing the gate length (L) while scaling the width (W) to maintain the same Rds for constant insertion loss. We show that the magnitude of the 3rd derivative and IIP3 level off quickly with increasing L.