A CMOS 5GHz Image-Reject Receiver Front-End Architecture

A fully-integrated double quadrature heterodyne receiver front-end uses a two-stage Lange coupler and achieves a measured image rejection ratio >55 dB over a 200MHz bandwidth at 5.25 GHz without any tuning or trimming. It also features 23.5 dB gain, -79 dBm sensitivity, 5.6 dB SSB noise figure, -7 dBm IIP3, -18dB S
_II
and 1mm x 2mm chip area in 0.18 μm CMOS.