2 GHz CMOS Voltage-Controlled Oscillator with Optimal Design of Phase Noise and Power Dissipation

An RF VCO design optimization strategy to achieve low phase noise and low bias current is presented for a cross-coupled LC-tuned CMOS oscillator topology. The impact of differential pair transistors' mode of operation and loading effects on the oscillator phase noise are investigated. The study shows that an optimal trade-off between thermal-noise-induced phase noise and DC power dissipation can be achieved when the oscillation amplitude is designed to set the differential pair transistors to operate at the boundary between saturation and triode regions. This design technique is employed to demonstrate a 2 GHz VCO achieving a low phase noise of -103dBc/Hz at 100kHz offset frequency while dissipating 2.67mA bias current from a 1.8V supply in a standard 0.18 μm CMOS process. The optimization strategy can be applied for other VCO design architectures to further enhance wireless communication system performance and battery lifetime.